EPFL engineers develop a computer chip with two heads

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Brian Adam
Professional Blogger, V logger, traveler and explorer of new horizons.

A team of engineers from the Laboratory of Electronics and Nanoscale Structures (LANES) of the Federal Polytechnic School of Lausanne (EPFL) of Switzerland, they have devised a chip two-head computer systems, meaning that these units group two functions, “logical operations and data storage” in a single design.

The creation of this chip promises more efficient electronic devices, with higher speeds in the execution of their processes, and therefore a higher performance of resources.

An alternative to Von Neumann architecture

Currently, logical functions and data storage are performed independently on separate drives, so data “must constantly be transferred between the two drives.” This action affects the functioning of the equipment, which tends to consume more time and energy, having to execute more processes.

However, the revolutionary chip presented by EPFL engineers represents an alternative to the Von Neumann architecture, by executing both functions under the same architecture.

This small device is made up of MoS2, a “two-dimensional material consisting of a single layer only three atoms thick”, making it an excellent semiconductor, ideal for dual execution of logic and storage processes.

Thanks to the inclusion of floating gate field effect transistors (FGFETs), these chips can hold electrical charges for longer periods of time, compared to a basic chip.

The operation of the two-head chips resembles that of the human brain

The director of LANES, Andras Kis expressed that the “capacity of circuits” to carry out simultaneous operations is similar to the functioning of the human brain.

He added that our “neurons are involved both in storing memories and in performing mental calculations.” It is presumed that this particularity is what makes these chips a great option for systems based on artificial intelligence. Kis added that:

“Our circuit design has several advantages. It can reduce the power loss associated with transferring data between memory units and processors, reduce the amount of time required for computing operations, and reduce the amount of space required. That opens the door to devices that are smaller, more powerful and more energy efficient. “

Like the silicon processor, this novel chip developed by the LANES research team promises improvements in next-generation smart devices.

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